The Mythical One-Cycle L1 Cache in
(ISCA) Papers
The problem
- CPU Caches have been a major component of ISCA papers for years
- At ISCA, most academic researchers do not have the resources to design/build
a full CPU, so their research is limited to using "simulators" to
attempt to model the behavior of modern processors.
- Part of this design is a cache simulator
- Often these papers will say the cache parameters used, and for some
reason they say they have L1 Caches with a latency of 1-cycle
- A typical cache latency these days is in the 3-4 cycle latency or worse.
It has been decades (due to the Memory Wall) that any processor
could maintain a 1-cycle latency.
- Any paper that uses 1-cycle latency for the L1 cache is overstating
the speed of a critical component by a factor of 4x.
- Even intro computer-architecture undergrads know this.
- Therefore any paper that uses this as part of their methodology is
wrong and should be withdrawn.
- It is mind-boggling that at a "top" conference like ISCA this would
appear in papers, let alone get through the review process.
References
There are various places you can find lists of cache latencies
for a wide variety of processors and see that 1-cycle L1 caches
haven't been common since the 1990s.
List of papers using this methodology:
Back to our ISCA methodology investigation page